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low power differential adc driver ada4932-1/ada4932-2 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features high performance at low power high speed ?3 db bandwidth of 560 mhz, g = 1 0.1 db gain flatness to 300 mhz slew rate: 2800 v/s, 25% to 75% fast 0.1% settling time of 9 ns low power: 9.6 ma per amplifier low harmonic distortion 100 db sfdr @ 10 mhz 90 db sfdr @ 20 mhz low input voltage noise: 3.6 nv/hz 0.5 mv typical input offset voltage externally adjustable gain can be used with fractional differential gains differential-to-differential or single-ended-to-differential operation adjustable output common-mode voltage input common-mode range shifted down by 1 v be wide supply range: +3 v to 5 v available in 16-lead and 24-lead lfcsp packages applications adc drivers single-ended-to-differential converters if and baseband gain blocks differential buffers line drivers general description the ada4932-x is the next gene ration ad8132 with higher performance, and lower noise and power consumption. it is an ideal choice for driving high performance adcs as a single-ended- to-differential or differential-to-differential amplifier. the output common-mode voltage is user adjustable by means of an internal common-mode feedback loop, allowing the ada4932-x output to match the input of the adc. the internal feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. with the ada4932-x, differential gain configurations are easily realized with a simple external four-resistor feedback network that determines the closed-loop gain of the amplifier. the ada4932-x is fabricated using the analog devices, inc., proprietary silicon-germanium (sige) complementary bipolar process, enabling it to achieve low levels of distortion and noise at low power consumption. the low offset and excellent dynamic performance of the ada4932-x make it well suited for a wide variety of data acquisition and signal processing applications. functional block diagrams 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ada4932-1 07752-001 figure 1. ada4932-1 ada4932-2 1 ?in1 2 +fb1 3 +v s1 4 +v s1 5 ?fb2 6 +in2 15 ?v s2 16 ?v s2 17 v ocm1 18 +out1 14 pd2 13 ?out2 7 ? i n 2 8 + f b 2 9 + v s 2 1 1 v o c m 2 1 2 + o u t 2 1 0 + v s 2 2 1 ? v s 1 2 2 ? v s 1 2 3 ? f b 1 2 4 + i n 1 2 0 p d 1 1 9 ? o u t 1 07752-002 figure 2. ada4932-2 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m harmonic distortion (dbc) frequency (hz) v out, dm = 2v p-p 07752-003 hd2, g = 1 hd3, g = 1 hd2, g = 2 hd3, g = 2 figure 3. harmonic distortion vs. frequency at various gains the ada4932-x is available in a pb-free, 3 mm 3 mm 16-lead lfcsp (ada4932-1, single) or a pb-free, 4 mm 4 mm 24-lead lfcsp (ada4932-2, dual). the pinout has been optimized to facilitate pcb layout and minimize distortion. the ada4932-1 and the ada4932-2 are specified to operate over the ?40c to +105c temperature range; both operate on supplies between +3 v and 5 v.
ada4932-1/ada4932-2 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v operation ............................................................................. 3 ? 5 v operation ............................................................................... 5 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? maximum power dissipation ..................................................... 7 ? esd caution .................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? typical performance characteristics ............................................. 9 ? test circuits ..................................................................................... 17 ? terminology .................................................................................... 18 ? theory of operation ...................................................................... 19 ? applications information .............................................................. 20 ? analyzing an application circuit ............................................ 20 ? setting the closed-loop gain .................................................. 20 ? estimating the output noise voltage ...................................... 20 ? impact of mismatches in the feedback networks ................. 21 ? calculating the input impedance for an application circuit .......................................................................................... 21 ? input common-mode voltage range ..................................... 23 ? input and output capacitive ac coupling ............................ 23 ? setting the output common-mode voltage .......................... 23 ? layout, grounding, and bypassing .............................................. 24 ? high performance adc driving ................................................. 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 26 ? revision history 8/09rev. 0 to rev. a changes to features section............................................................ 1 changes to figure 11 ........................................................................ 9 changes to figure 43 and figure 45 ............................................. 15 changes to figure 52, figure 53, and figure 54 ......................... 17 10/08revision 0: initial version
ada4932-1/ada4932-2 rev. a | page 3 of 28 specifications 5 v operation t a = 25c, +v s = 5 v, ?v s = ?5 v, v ocm = 0 v, r f = 499 , r g = 499 , r t = 53.6 (when used), r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. refer to figure 55 for signal definitions. d in to v out, dm performance tale parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out, dm = 0.1 v p-p 560 mhz v out, dm = 0.1 v p-p, r f = r g = 205 1000 mhz ?3 db large signal bandwidth v out, dm = 2.0 v p-p 360 mhz v out, dm = 2.0 v p-p, r f = r g = 205 360 mhz bandwidth for 0.1 db flatness v out, dm = 2.0 v p-p, ada4932-1, r l = 200 300 mhz v out, dm = 2.0 v p-p, ada4932-2, r l = 200 100 mhz slew rate v out, dm = 2 v p-p, 25% to 75% 2800 v/s settling time to 0.1% v out, dm = 2 v step 9 ns overdrive recovery time v in = 0 v to 5 v ramp, g = 2 20 ns noise/harmonic performance see figure 54 for distortion test circuit second harmonic v out, dm = 2 v p-p, 1 mhz ?110 dbc v out, dm = 2 v p-p, 10 mhz ?100 dbc v out, dm = 2 v p-p, 20 mhz ?90 dbc v out, dm = 2 v p-p, 50 mhz ?72 dbc third harmonic v out, dm = 2 v p-p, 1 mhz ?130 dbc v out, dm = 2 v p-p, 10 mhz ?120 dbc v out, dm = 2 v p-p, 20 mhz ?105 dbc v out, dm = 2 v p-p, 50 mhz ?80 dbc imd f 1 = 30 mhz, f 2 = 30.1 mhz, v out, dm = 2 v p-p ?91 dbc voltage noise (rti) f = 1 mhz 3.6 nv/hz input current noise f = 1 mhz 1.0 pa/hz crosstalk f = 10 mhz, ada4932-2 ?100 db input characteristics offset voltage v +din = v ?din = v ocm = 0 v ?2.2 0.5 +2.2 mv t min to t max variation ?3.7 v/c input bias current ?5.2 ?2.5 ?0.1 a t min to t max variation ?9.5 na/c input offset current ?0.2 0.025 +0.2 a input resistance differential 11 m common mode 16 m input capacitance 0.5 pf input common-mode voltage range ?v s + 0.2 to +v s ? 1.8 v cmrr ?v out, dm /?v in, cm , ?v in, cm = 1 v ?100 ?87 db open-loop gain 64 66 db output characteristics output voltage swing maximum ?v out , single-ended output, r f = r g = 10 k, r l = 1 k ?v s + 1.4 to +v s ? 1.4 ?v s + 1.2 to +v s ? 1.2 v linear output current 200 khz, r l, dm = 10 , sfdr = 68 db 80 ma rms output balance error ?v out, cm /?v out, dm , ?v out, dm = 2 v p-p, 1 mhz, see figure 53 for output balance test circuit ?64 ?60 db
ada4932-1/ada4932-2 rev. a | page 4 of 28 v ocm to v out, cm performance table 2. parameter conditions min typ max unit v ocm dynamic performance ?3 db small signal bandwidth v out, cm = 100 mv p-p 270 mhz ?3 db large signal bandwidth v out, cm = 2 v p-p 105 mhz slew rate v in = 1.5 v to 3.5 v, 25% to 75% 410 v/s input voltage noise (rti) f = 1 mhz 9.6 nv/hz v ocm input characteristics input voltage range ?v s + 1.2 to +v s ? 1.2 v input resistance 22 25 29 k input offset voltage v +din = v ?din = 0 v ?5.1 1 +5.1 mv v ocm cmrr v out, dm /v ocm , v ocm = 1 v ?100 ?86 db gain v out, cm /v ocm , v ocm = 1 v 0.995 0.998 1.000 v/v general performance table 3. parameter conditions min typ max unit power supply operating range 3.0 11 v quiescent current per amplifier 9.0 9.6 10.1 ma t min to t max variation 35 a/c powered down 0.9 1.0 ma power supply rejection ratio v out, dm /v s , v s = 1 v p-p ?96 ?84 db power-down (pd ) pd input voltage powered down (+v s ? 2.5) v enabled (+v s ? 1.8) v turn-off time 1100 ns turn-on time 16 ns pd pin bias current per amplifier enabled pd = 5 v ?10 +0.7 +10 a disabled pd = 0 v ?240 ?195 ?140 a operating temperature range ?40 +105 c
ada4932-1/ada4932-2 rev. a | page 5 of 28 5 v operation t a = 25c, +v s = 5 v, ?v s = 0 v, v ocm = 2.5 v, r f = 499 , r g = 499 , r t = 53.6 (when used), r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. refer to figure 55 for signal definitions. d in to v out, dm performance tale parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out, dm = 0.1 v p-p 560 mhz v out, dm = 0.1 v p-p, r f = r g = 205 990 mhz ?3 db large signal bandwidth v out, dm = 2.0 v p-p 315 mhz v out, dm = 2.0 v p-p, r f = r g = 205 320 mhz bandwidth for 0.1 db flatness v out, dm = 2.0 v p-p, ada4932-1, r l = 200 120 mhz v out, dm = 2.0 v p-p, ada4932-2, r l = 200 200 mhz slew rate v out, dm = 2 v p-p, 25% to 75% 2200 v/s settling time to 0.1% v out, dm = 2 v step 10 ns overdrive recovery time v in = 0 v to 2.5 v ramp, g = 2 20 ns noise/harmonic performance see figure 54 for distortion test circuit second harmonic v out, dm = 2 v p-p, 1 mhz ?110 dbc v out, dm = 2 v p-p, 10 mhz ?100 dbc v out, dm = 2 v p-p, 20 mhz ?90 dbc v out, dm = 2 v p-p, 50 mhz ?72 dbc third harmonic v out, dm = 2 v p-p, 1 mhz ?120 dbc v out, dm = 2 v p-p, 10 mhz ?100 dbc v out, dm = 2 v p-p, 20 mhz ?87 dbc v out, dm = 2 v p-p, 50 mhz ?70 dbc imd f 1 = 30 mhz, f 2 = 30.1 mhz, v out, dm = 2 v p-p ?91 dbc voltage noise (rti) f = 1 mhz 3.6 nv/hz input current noise f = 1 mhz 1.0 pa/hz crosstalk f = 10 mhz, ada4932-2 ?100 db input characteristics offset voltage v +din = v ?din = v ocm = 2.5 v ?2.2 0.5 +2.2 mv t min to t max variation ?3.7 v/c input bias current ?5.3 ?3.0 ?0.23 a t min to t max variation ?9.5 na/c input offset current ?0.25 0.025 +0.25 a input resistance differential 11 m common mode 16 m input capacitance 0.5 pf input common-mode voltage range ?v s + 0.2 to +v s ? 1.8 v cmrr ?v out, dm /?v in, cm , ?v in, cm = 1 v ?100 ?87 db open-loop gain 64 66 db output characteristics output voltage swing maximum ?v out , single-ended output, r f = r g = 10 k, r l = 1 k ?v s + 1.15 to +v s ? 1.15 ?v s + 1.02 to +v s ? 1.02 v linear output current 200 khz, r l, dm = 10 , sfdr = 67 db 53 ma rms output balance error ?v out, cm /?v out, dm , ?v out, dm = 1 v p-p, 1 mhz, see figure 53 for output balance test circuit ?64 ?60 db
ada4932-1/ada4932-2 rev. a | page 6 of 28 v ocm to v out, cm performance table 5. parameter conditions min typ max unit v ocm dynamic performance ?3 db small signal bandwidth v out, cm = 100 mv p-p 260 mhz ?3 db large signal bandwidth v out, cm = 2 v p-p 90 mhz slew rate v in = 1.5 v to 3.5 v, 25% to 75% 360 v/s input voltage noise (rti) f = 1 mhz 9.6 nv/hz v ocm input characteristics input voltage range ?v s + 1.2 to +v s ? 1.2 v input resistance 22 25 29 k input offset voltage v +din = v ?din = 2.5 v ?6.5 ?3.0 +6.5 mv v ocm cmrr v out, dm /v ocm , v ocm = 1 v ?100 ?86 db gain v out, cm /v ocm , v ocm = 1 v 0.995 0.998 1.000 v/v general performance table 6. parameter conditions min typ max unit power supply operating range 3.0 11 v quiescent current per amplifier 8.2 8.8 9.5 ma t min to t max variation 35 a/c powered down 0.7 0.8 ma power supply rejection ratio v out, dm /v s , v s = 1 v p-p ?96 ?84 db power-down (pd ) pd input voltage powered down (+v s ? 2.5) v enabled (+v s ? 1.8) v turn-off time 1100 ns turn-on time 16 ns pd pin bias current per amplifier enabled pd = 5 v ?10 +0.7 +10 a disabled pd = 0 v ?100 ?70 ?40 a operating temperature range ?40 +105 c
ada4932-1/ada4932-2 rev. a | page 7 of 28 absolute maximum ratings table 7. parameter rating supply voltage 11 v power dissipation see figure 4 input current, +in, ?in, pd 5 ma storage temperature range ?65c to +125c operating temperature range ada4932-1 ?40c to +105c ada4932-2 ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in eia/jesd 51-7. table 8. thermal resistance package type ja unit ada4932-1, 16-lead lfcsp (exposed pad) 91 c/w ada4932-2, 24-lead lfcsp (exposed pad) 65 c/w maximum power dissipation the maximum safe power dissipation in the ada4932-x package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4932-x. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead lfcsp (91c/w) and the dual 24-lead lfcsp (65c/w) on a jedec standard 4-layer board with the exposed pad soldered to a pcb pad that is connected to a solid plane. 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 ?40 100 80 60 40 20 0 ?20 maximum power dissipation (w) ambient temperature (c) ada4932-1 ada4932-2 07752-204 figure 4. maximum power dissipation vs. ambient temperature for a 4-layer board esd caution
ada4932-1/ada4932-2 rev. a | page 8 of 28 pin configurations and function descriptions 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ada4932-1 top view (not to scale) pin 1 indicator 07752-005 notes 1. solder exposed paddle on back of package to ground plane or to a power plane. figure 5. ada4932-1 pin configuration pin 1 indicator 1 2 3 4 5 6 15 16 17 18 14 13 7 8 9 1 1 1 2 1 0 2 1 2 2 2 3 2 4 + i n 1 2 0 1 9 top view (not to scale) ada4932-2 ?in1 + fb1 +v s1 +v s1 ? fb2 +in2 ?v s2 ?v s2 v ocm1 +out1 pd2 ?out2 ? i n 2 + f b 2 + v s 2 v o c m 2 + o u t 2 + v s 2 ? v s 1 ? v s 1 ? f b 1 p d 1 ? o u t 1 07752-006 notes 1. solder exposed paddle on back of package to ground plane or to a power plane. figure 6. ada4932-2 pin configuration table 9. ada4932-1 pin function descriptions pin no. mnemonic description 1 ?fb negative output for feedback component connection. 2 +in positive input summing node. 3 ?in negative input summing node. 4 +fb positive output for feedback component connection. 5 to 8 +v s positive supply voltage. 9 v ocm output common-mode voltage. 10 +out positive output for load connection. 11 ?out negative output for load connection. 12 pd power-down pin. 13 to 16 ?v s negative supply voltage. 17 (epad) exposed paddle (epad) solder the exposed paddle on the back of the package to a ground plane or to a power plane. table 10. ada4932-2 pin function descriptions pin no. mnemonic description 1 ?in1 negative input summing node 1. 2 +fb1 positive output feedback 1. 3, 4 +v s1 positive supply voltage 1. 5 ?fb2 negative output feedback 2. 6 +in2 positive input summing node 2. 7 ?in2 negative input summing node 2. 8 +fb2 positive output feedback 2. 9, 10 +v s2 positive supply voltage 2. 11 v ocm2 output common-mode voltage 2. 12 +out2 positive output 2. 13 ?out2 negative output 2. 14 pd2 power-down pin 2. 15, 16 ?v s2 negative supply voltage 2. 17 v ocm1 output common-mode voltage 1. 18 +out1 positive output 1. 19 ?out1 negative output 1. 20 pd1 power-down pin 1. 21, 22 ?v s1 negative supply voltage 1. 23 ?fb1 negative output feedback 1. 24 +in1 positive input summing node 1. 25 (epad) exposed paddle (epad) solder the exposed paddle on the back of the package to a ground plane or to a power plane.
ada4932-1/ada4932-2 rev. a | page 9 of 28 typical performance characteristics t a = 25c, +v s = 5 v, ?v s = ?5 v, v ocm = 0 v, r g = 499 , r f = 499 , r t = 53.6 (when used), r l, dm = 1 k, unless otherwise noted. refer to figure 52 for test setup. refer to figure 55 for signal definitions. ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g normalized closed-loop gain (db) frequency (hz) v in = 100mv p-p r f = 499 ? r g =499 ? , 249 ? 07752-007 gain = 1 gain = 2 figure 7. small signal frequency response for various gains ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g 10g closed-loop gain (db) frequency (hz) r f =r g =499 ? r f =r g =205 ? v out, dm = 100mv p-p 07752-008 figure 8. small signal frequency response for various r f and r g ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 100mv p-p 07752-009 v s = 5v v s = 2.5v figure 9. small signal frequency response for various supplies ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g frequency (hz) v in = 2v p-p r f = 499 ? r g =499 ? , 249 ? 07752-010 gain = 1 gain = 2 normalized closed-loop gain (db) figure 10. large signal frequency response for various gains ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1k closed-loop gain (db) frequency (mhz) v out, dm = 2v p-p r f = r g = 205 ? r f = r g = 499 ? 07752-058 figure 11. large signal frequency response for various r f and r g ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 2v p-p 07752-012 v s = 5v v s = 2.5v figure 12. large signal frequenc y response for various supplies
ada4932-1/ada4932-2 rev. a | page 10 of 28 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop g a in (db) frequency (hz) v out, dm = 100mv p-p 07752-013 t a =?40c t a = +25c t a = +105c figure 13. small signal frequency response for various temperatures ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 100mv p-p 07752-014 r l = 1k ? r l = 200 ? figure 14. small signal frequency response at various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 100mv p-p 07752-015 v ocm =0v v ocm = +2.5v v ocm = ?2.5v figure 15. small signal frequency response for various v ocm levels ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 2v p-p 07752-016 t a =?40c t a = +25c t a = +105c figure 16. large signal frequency response for various temperatures ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 2v p-p 07752-017 r l = 1k ? r l = 200 ? figure 17. large signal frequency response at various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 2v p-p 07752-018 v ocm =0v v ocm = +2.5v v ocm = ?2.5v figure 18. large signal frequency response for various v ocm levels
ada4932-1/ada4932-2 rev. a | page 11 of 28 ?8 ?6 ?4 ?2 0 2 4 1m 10m 100m 1g 10g closed-loop gain (db) frequency (hz) v out, dm = 100mv p-p 07752-019 c l =0pf c l =0.9pf c l =1.8pf figure 19. small signal frequency response at various capacitive loads ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 100mv p-p 07752-020 ada4932-1, r l = 1k ? ada4932-1, r l = 200 ? ada4932-2, ch 1, r l = 1k ? ada4932-2, ch 1, r l = 200 ? ada4932-2, ch 2, r l = 1k ? ada4932-2, ch 2, r l = 200 ? figure 20. 0.1 db flatness small signal frequency response for various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1m 10m 100m 1g v ocm gain (db) frequency (hz) v out, cm = 100mv p-p 07752-021 v ocm (dc) = 0v v ocm (dc) = +2.5v v ocm (dc) = ?2.5v figure 21. v ocm small signal frequency response at various dc levels ?10 ?8 ?6 ?4 ?2 0 2 4 10m 100m 1g closed-loop gain (db) frequency (hz) c l =0pf c l =0.9pf c l =1.8pf 07752-022 v out, dm = 2v p-p figure 22. large signal frequency response at various capacitive loads ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1m 10m 100m 1g closed-loop gain (db) frequency (hz) v out, dm = 2v p-p 07752-023 ada4932-1, r l = 1k ? ada4932-1, r l = 200 ? ada4932-2, ch 1, r l = 1k ? ada4932-2, ch 1, r l = 200 ? ada4932-2, ch 2, r l = 1k ? ada4932-2, ch 2, r l = 200 ? figure 23. 0.1 db flatness large signal frequency response for various loads 2 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 v ocm gain (db) frequency (hz) v out, cm = 2v p-p 1m 1g 100m 10m v ocm (dc) = 0v v ocm (dc) = +2.5v v ocm (dc) = ?2.5v 07752-224 figure 24. v ocm large signal frequency response at various dc levels
ada4932-1/ada4932-2 rev. a | page 12 of 28 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m harmonic distortion (dbc) frequency (hz) v out, dm = 2v p-p 07752-025 hd2, r l =1k ? hd3, r l =1k ? hd2, r l =200 ? hd3, r l =200 ? figure 25. harmonic distortion vs. frequency at various loads ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m harmonic distortion (dbc) frequency (hz) 07752-026 hd2, 5.0v hd3, 5.0v hd2, 2.5v hd3, 2.5v v out, dm = 2v p-p v ocm = 0v figure 26. harmonic distortion vs. frequency at various supplies ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 ?4 ?3 ?2 ?1 0 1 2 3 4 harmonic distortion (dbc) v ocm (v p-p) 07752-027 v out = 2v p-p hd2 at 10mhz hd3 at 10mhz hd2 at 30mhz hd3 at 30mhz figure 27. harmonic distortion vs. v ocm at various frequencies, 5 v supplies ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m harmonic distortion (dbc) frequency (hz) v out, dm = 2v p-p 07752-028 hd2, g = 1 hd3, g = 1 hd2, g = 2 hd3, g = 2 figure 28. harmonic distortion vs. frequency at various gains ?130 ?140 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 01 3 2 45678910 harmonic distortion (dbc) v out, dm (v p-p) 07752-029 v ocm = 0v hd2, 5.0v hd3, 5.0v hd2, 2.5v hd3, 2.5v figure 29. harmonic distortion vs. v out, dm and supply voltage, f = 10 mhz ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 1.4 1.6 2.0 1.8 2.2 2.4 2.6 2.8 3.0 3.2 3.4 harmonic distortion (dbc) v ocm (v) 07752-030 v out = 2v p-p hd2 at 10mhz hd3 at 10mhz hd2 at 30mhz hd3 at 30mhz figure 30. harmonic distortion vs. v ocm at various frequencies, +5 v supply
ada4932-1/ada4932-2 rev. a | page 13 of 28 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m harmonic distortion (dbc) frequency (hz) 07752-031 hd2, 2v p-p hd3, 2v p-p hd2, 4v p-p hd3, 4v p-p figure 31. harmonic distortion vs. frequency at various v out, dm ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m spurious-free dynamic range (dbc) frequency (hz) v out, dm = 2v p-p 07752-032 r l = 200 ? r l = 1k ? figure 32. spurious-free dynamic range vs. frequency at various loads ?100 ?90 ?80 ?60 ?70 ?50 ?40 ?30 ? 20 1m 10m 100m 1g cmmr (db) frequency (hz) 07752-033 r l, dm = 200 ? figure 33. cmrr vs. frequency ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 100k 1m 10m 100m harmonic distortion (dbc) frequency (hz) v out, dm = 2v p-p 07752-034 hd2, r f =r g =499 ? hd3, r f =r g =499 ? hd2, r f =r g =200 ? hd3, r f =r g =200 ? figure 34. harmonic distortion vs. frequency at various r f and r g 10 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 normalized spectrum (dbc) frequency (mhz) v out, dm = 2v p-p 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 07752-235 figure 35. 30 mhz intermodulation distortion ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1m 10m 100m 1g pssr (db) frequency (hz) r l, dm = 200 ? 07752-036 ?psrr +psrr figure 36. psrr vs. frequency
ada4932-1/ada4932-2 rev. a | page 14 of 28 ? 10 ?70 ?60 ?50 ?40 ?30 ?20 1m 1g 100m 10m output balance (db) frequency (hz) r l, dm = 200 ? 07752-237 figure 37. output balance vs. frequency ?60 ?50 ?40 ?30 ?20 ?10 0 1m 10m 100m 1g s-parameters (db) frequency (hz) 07752-038 r l = 200 ? input single-ended, 50 ? load termination output differential, 100 ? source termination s11: common-mode-to-common-mode s22: differential-to-differential s11 s22 figure 38. return loss (s 11 , s 22 ) vs. frequency 1 10 100 10 100 input voltage noise (nv/ hz) frequency (hz) 1k 10k 100k 1m 07752-039 figure 39. voltage noise spectral density, referred to input 80 ?80 ?60 ?40 ?20 0 20 40 60 90 ?270 ?225 ?180 ?135 ?90 ?45 0 45 1k 10k 100k 1m 10m 100m 1g 10g gain (db) phase (degrees) frequency (hz) gain phase 07752-240 figure 40. open-loop gain and phase vs. frequency 100 10 1 0.1 output impedance ( ? ) frequency (hz) 100k 1g 100m 10m 1m 07752-241 figure 41. closed-loop output impeda nce magnitude vs. frequency, g = 1 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 voltage (v) time (ns) 0 100 200 300 400 500 600 700 800 900 1000 2 v in v out, dm 07752-242 figure 42.overdrive recovery, g = 2
ada4932-1/ada4932-2 rev. a | page 15 of 28 0 5 10 15 20 25 30 output voltage (v) time (ns) 0 7752-059 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 figure 43. small signal pulse response 0.08 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 output voltage (v) time (ns) 030 25 20 15 10 5 c l = 0pf c l = 0.9pf c l = 1.8pf 07752-244 figure 44. small signal pulse response for various capacitive loads ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0 5 10 15 20 25 30 output voltage (v) time (ns) 07752-060 figure 45. v ocm small signal pulse response 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 5 10 15 20 25 30 output voltage (v) time (ns) 07752-146 figure 46. large signal pulse response 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 output voltage (v) time (ns) 030 25 20 15 10 5 c l = 0pf c l = 0.9pf c l = 1.8pf 07752-247 figure 47. large signal pulse response for various capacitive loads 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 5 10 15 20 25 30 output voltage (v) time (ns) 07752-148 figure 48. v ocm large signal pulse response
ada4932-1/ada4932-2 rev. a | page 16 of 28 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 02468101214161820 error (%) voltage (v) time (ns) input output error 07752-149 figure 49. settling time ?160 ?140 ?120 ?100 ?80 ?40 ?60 ?20 0 1m 10m 100m 1g crosstalk (db) frequency (hz) 07752-150 v out, dm = 2v p-p r l, dm = 200 ? channel 1 to channel 2 channel 2 to channel 1 figure 50. crosstalk vs. frequency, ada4932-2 1.2 ?0.2 0.2 0 0.4 0.6 0.8 1.0 6 ?1 1 0 2 3 4 5 output voltage (v) pd voltage (v) time (s) 06 5 4 3 2 1 r l, dm = 200 ? v on pd 07752-252 figure 51. pd response time
ada4932-1/ada4932-2 rev. a | page 17 of 28 test circuits ada4932-x 1k? +5v ?5v 499 ? 499? 50? dc-coupled generator 499 ? 499 ? v ocm 53.6 ? 25.5 ? v in 07752-043 figure 52. equivalent basic test circuit, g = 1 ada4932-x +5v 0.1f ?5v 499 ? 499? 50? 499? networ k analyzer input network analyzer input network analyzer output ac-coupled 50? 50? 499 ? 49.9 ? 49.9 ? v ocm 53.6 ? v in 07752-044 25.5 ? figure 53. test circuit for output balance, cmrr ada4932-x +5v ?5v 499 ? 499 ? 50? 499 ? 442 ? 442 ? 499 ? v ocm 53.6 ? 261 ? 200 ? hp lp 2:1 50? ct v in low-pass filter dc-coupled generator 0.1f 0.1f dual filter 07752-045 25.5 ? figure 54. test circuit for distortion measurements
ada4932-1/ada4932-2 rev. a | page 18 of 28 terminology +in ?in +out ?out +d in ? fb +fb ?d in v ocm r g r f r g v out, dm r l, dm r f ada4932-x 07752-046 figure 55. signal and circuit definitions differential voltage differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or equivalently, output differential mode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out terminals with respect to a common ground reference. similarly, the differential input voltage is defined as v in, dm = ( +d in ? ( ?d in )) common-mode voltage common-mode voltage refers to the average of two node voltages with respect to the local ground reference. the output common- mode voltage is defined as v out, cm = ( v +out + v ?out )/2 balance output balance is a measure of how close the output differential signals are to being equal in amplitude and opposite in phase. output balance is most easily determined by placing a well- matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see figure 53). by this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. dmout cmout v v error balance output , , ? ? ?
ada4932-1/ada4932-2 rev. a | page 19 of 28 theory of operation the ada4932-x differs from conven tional op amps in that it has two outputs whose voltages move in opposite directions and an additional input, v ocm . like an op amp, it relies on high open- loop gain and negative feedback to force these outputs to the desired voltages. the ada4932-x behaves much like a standard voltage feedback op amp and facilitates single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. like an op amp, the ada4932-x has high input impedance and low output impedance. because it uses voltage feedback, the ada4932-x manifest s a nominally constant gain bandwidth product. two feedback loops are employed to control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls only the differential output voltage. the common-mode feedback controls only the common-mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. the output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the v ocm input. the internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. this results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180 apart in phase.
ada4932-1/ada4932-2 rev. a | page 20 of 28 applications information analyzing an application circuit the ada4932-x uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and ?in (see figure 55). for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common-mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these principles, any applica- tion circuit can be analyzed. setting the closed-loop gain using the approach described in the analyzing an application circuit section, the differential gain of the circuit in figure 55 can be determined by g f dmin dmout r r v v ? , , this presumes that the input resistors (r g ) and feedback resistors (r f ) on each side are equal. estimating the output noise voltage the differential output noise of the ada4932-x can be estimated using the noise model in figure 56. the input- referred noise voltage density, v nin , is modeled as a differential input, and the noise currents, i nin? and i nin+ , appear between each input and ground. the output voltage due to v nin is obtained by multiplying v nin by the noise gain, g n (defined in the g n equation that follows). the noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. the noise voltage density at the v ocm pin is v ncm . when the feedback networks have the same feedback factor, as is true in most cases, the output noise due to v ncm is common mode. each of the four resistors contributes (4ktr xx ) 1/2 . the noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multip- lied by r f /r g . table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. ada4932-x + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? 07752-047 figure 56. noise model table 11. output noise voltag e density calculations for matched feedback networks input noise contribution input noise term input noise voltage density output multiplication factor differential output noise voltage density term differential input v nin v nin g n v no1 = g n (v nin ) inverting input i nin? i nin? (r f2 ) 1 v no2 = (i nin? )(r f2 ) noninverting input i nin+ i nin+ (r f1 ) 1 v no3 = (i nin+ )(r f1 ) v ocm input v ncm v ncm 0 v no4 = 0 v gain resistor, r g1 v nrg1 (4ktr g1 ) 1/2 r f1 /r g1 v no5 = (r f1 /r g1 )(4ktr g1 ) 1/2 gain resistor, r g2 v nrg2 (4ktr g2 ) 1/2 r f2 /r g2 v no6 = (r f2 /r g2 )(4ktr g2 ) 1/2 feedback resistor, r f1 v nrf1 (4ktr f1 ) 1/2 1 v no7 = (4ktr f1 ) 1/2 feedback resistor, r f2 v nrf2 (4ktr f2 ) 1/2 1 v no8 = (4ktr f2 ) 1/2 table 12. differential input, dc-coupled nominal gain (db) r f () r g () r in, dm () differential output noise density (nv/hz) 0 499 499 998 9.25 6 499 249 498 12.9 10 768 243 486 18.2 table 13. single-ended ground-referenced input, dc-coupled, r s = 50 nominal gain (db) r f () r g1 () r t () (std 1%) r in, cm () r g2 () 1 differential output noise density (nv/hz) 0 511 499 53.6 665 525 9.19 6 523 249 57.6 374 276 12.6 10 806 243 57.6 392 270 17.7 1 r g2 = r g1 + (r s ||r t ).
ada4932-1/ada4932-2 rev. a | page 21 of 28 similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the input- referred terms at +in and ?in by the appropriate output factor, where: ?? 21 n | g ? ? 2 is the circuit noise gain. g1 f1 g1 1 rr r ? ? and g2 f2 g2 2 rr r ? ? are the feedback factors. when the feedback factors are matched, r f1 /r g1 = r f2 /r g2 , 1 = 2 = , and the noise gain becomes g f n r r g ??? 1 1 note that the output noise from v ocm goes to zero in this case. the total differential output noise density, v nod , is the root-sum- square of the individual output noise terms. ? ? ? 8 1i 2 noi nod vv table 12 and table 13 list several common gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. impact of mismatches in the feedback networks as previously mentioned, even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remain equal and 180 out of phase. the input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. the gain from the v ocm pin to v out, dm is equal to 2( 1 ? 2 )/( 1 + 2 ) when 1 = 2 , this term goes to zero and there is no differential output voltage due to the voltage on the v ocm input (including noise). the extreme case occurs when one loop is open and the other has 100% feedback; in this case, the gain from v ocm input to v out, dm is either +2 or ?2, depending on which loop is closed. the feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the v ocm input are negligible. if the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from v ocm to v out, dm and account for the extra noise. for example, if 1 = 0.5 and 2 = 0.25, the gain from v ocm to v out, dm is 0.67. if the v ocm pin is set to 2.5 v, a differential offset voltage is present at the output of (2.5 v)(0.67) = 1.67 v. the differential output noise contribution is (9.6 nv/hz)(0.67) = 6.4 nv/hz. both of these results are undesirable in most applications; therefore, it is best to use nominally matched feedback factors. mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. as a practical summarization of the above issues, resistors of 1% tolerance produce a worst-case input cmrr of approximately 40 db, a worst-case differential-mode output offset of 25 mv due to a 2.5 v v ocm input, negligible v ocm noise contribution, and no significant degradation in output balance error. calculating the input impedance for an application circuit the effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, as shown in figure 57, the input impedance (r in, dm ) between the inputs (+d in and ?d in ) is r in, dm = r g + r g = 2 r g . +v s ?v s +in ?in r f r f +d in ?d in v ocm r g r g v out, dm 07752-048 ada4932-x figure 57. ada4932-x configured for balanced (differential) inputs for an unbalanced, single-ended input signal (see figure 58), the input impedance is ?? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? f g f g sein rr r r r 2 1 , ada4932-x r l v out, dm +v s ?v s r g r g r f r f v ocm r in, se 0 7752-049 figure 58. ada4932-x with unbalanced (single-ended) input the input impedance of the circuit is effectively higher than it is for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor, r g . the common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider that is formed by r f and r g in the lower loop. this voltage is present at both
ada4932-1/ada4932-2 rev. a | page 22 of 28 input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across r g in the upper loop and partially bootstrapping r g . terminating a sing le-ended input this section describes how to properly terminate a single-ended input to the ada4932-x with a gain of 1, r f = 499 , and r g = 499 . an example using an input source with a terminated output voltage of 1 v p-p and source resistance of 50 illustrates the four steps that must be followed. note that because the terminated output voltage of the source is 1 v p-p, the open-circuit output voltage of the source is 2 v p-p. the source shown in figure 59 indicates this open-circuit voltage. 1. the input impedance is calculated using the formula 665 )499499(2 499 1 499 )(2 1 , ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? f g f g sein rr r r r r s 50? v s 2v p-p r in, se 665 ? ada4932-x r l v out, dm +v s ?v s r g 499 ? r g 499 ? r f 499? r f 499? v ocm 07752-050 figure 59. calculating single -ended input impedance, r in 2. to match the 50 source resistance, calculate the termination resistor, r t , using r t ||665 = 50 . the closest standard 1% value for r t is 53.6 . ada4932-x r l v out, dm +v s ?v s r s 50? r g 499? r g 499? r f 499? r f 499? v ocm v s 2v p-p r in, se 50? r t 53.6 ? 0 7752-051 figure 60. adding termination resistor, r t 3. figure 60 shows that the effective r g in the upper feedback loop is now greater than the r g in the lower loop due to the addition of the termination resistors. to compensate for the imbalance of the gain resistors, add a correction resistor (r ts ) in series with r g in the lower loop. r ts is the thevenin equivalent of the source resistance, r s , and the termination resistance, r t , and is equal to r s ||r t . r s 50 ? v s 2 v p- p r t 53.6 ? r th 25.9 ? v th 1.03v p-p 0 7752-052 figure 61. calculating the thevenin equivalent r ts = r th = r s ||r t = 25.9 . note that v th is greater than 1 v p-p, which was obtained with r t = 50 . the modified circuit with the thevenin equivalent (closest 1% value used for r th ) of the terminated source and r ts in the lower feedback loop is shown in figure 62. ada4932-x r l v out, dm +v s ?v s r th 25.5 ? r g 499? r g 499? r f 499 ? r f 499 ? v ocm v th 1.03v p-p r ts 25.5 ? 07752-053 figure 62. thevenin equivalent and matched gain resistors figure 62 presents a tractable circuit with matched feedback loops that can be easily evaluated. it is useful to point out two effects that occur with a termi- nated input. the first is that the value of r g is increased in both loops, lowering the overall closed-loop gain. the second is that v th is a little larger than 1 v p-p, as it would be if r t = 50 . these two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 k), the effects essentially cancel each other out. for small r f and r g , or high gains, however, the diminished closed-loop gain is not canceled completely by the increased v th . this can be seen by evaluating figure 62. the desired differential output in this example is 1 v p-p because the terminated input signal was 1 v p-p and the closed-loop gain = 1. the actual differential output voltage, however, is equal to (1.03 v p-p)(499/524.5) = 0.98 v p-p. to obtain the desired output voltage of 1 v p-p, a final gain adjustment can be made by increasing r f without modifying any of the input circuitry. this is discussed in step 4.
ada4932-1/ada4932-2 rev. a | page 23 of 28 4. the feedback resistor value is modified as a final gain adjustment to obtain the desired output voltage. to make the output voltage v out = 1 v p-p, calculate r f using the following formula: ?? ?? ???? ?? ? ?? ? ? ? 509 03.1 5.524 1 , ppv ppv v rrvdesired r th ts g dm out f the closest standard 1% value to 509 is 511 , which gives a differential output voltage of 1.00 v p-p. the final circuit is shown in figure 63. ada4932-x r l v out, dm 1.00v p-p +v s ?v s r s 50 ? r g 499? r g 499? r f 511 ? r f 511 ? v ocm v s 2v p-p 1v p-p r t 53.6 ? r ts 25.5 ? 07752-054 figure 63. terminated single-ende d-to-differential system with g = 2 input common-mode voltage range the ada4932-x input common-mode range is shifted down by approximately one vbe, in contrast to other adc drivers with centered input ranges such as the ada4939-x . the downward-shifted input common-mode range is especially suited to dc-coupled, single-ended-to-differential, and single- supply applications. for 5 v operation, the input common-mode range at the summing nodes of the amplifier is specified as ?4.8 v to +3.2 v, and is specified as +0.2 v to +3.2 v with a +5 v supply. to avoid nonlinearities, the voltage swing at the +in and ?in terminals must be confined to these ranges. input and output capacitive ac coupling while the ada4932-x is best suited to dc-coupled applications, it is nonetheless possible to use it in ac-coupled circuits. input ac coupling capacitors can be inserted between the source and r g . this ac coupling blocks the flow of the dc common-mode feedback current and causes the ada4932-x dc input common- mode voltage to equal the dc output common-mode voltage. these ac coupling capacitors must be placed in both loops to keep the feedback factors matched. output ac coupling capacitors can be placed in series between each output and its respective load. setting the output common-mode voltage the v ocm pin of the ada4932-x is internally biased with a vol- tage divider comprised of two 50 k resistors across the supplies, with a tap at a voltage approximately equal to the midsupply point, [(+v s ) + (?v s )]/2. because of this internal divider, the v ocm pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. relying on the internal bias results in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 . if an external voltage divider consisting of equal resistor values is used to set v ocm to midsupply with greater accuracy than produced internally, higher values can be used because the external resistors are placed in parallel with the internal resistors. the output common-mode offset listed in the specifications section assumes that the v ocm input is driven by a low impedance voltage source. it is also possible to connect the v ocm input to a common-mode level (cml) output of an adc; however, care must be taken to ensure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 10 k. if multiple ada4932-x devices share one adc reference output, a buffer may be necessary to drive the parallel inputs.
ada4932-1/ada4932-2 rev. a | page 24 of 28 layout, grounding, and bypassing as a high speed device, the ada4932-x is sensitive to the pcb environment in which it operates. realizing its superior performance requires attention to the details of high speed pcb design. the first requirement is a solid ground plane that covers as much of the board area around the ada4932-x as possible. however, the area near the feedback resistors (r f ), gain resistors (r g ), and the input summing nodes (pin 2 and pin 3) should be cleared of all ground and power planes (see figure 64). clearing the ground and power planes minimizes any stray capacitance at these nodes and thus minimizes peaking of the response of the amplifier at high frequencies. the thermal resistance, ja , is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in eia/jesd51-7. 0 7752-055 figure 64. ground and power plane voiding in vicinity of r f and r g bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. high frequency ceramic chip capacitors should be used. it is recommended that two parallel bypass capacitors (1000 pf and 0.1 f) be used for each supply. place the 1000 pf capacitor closer to the device. further away, provide low frequency bulk bypassing using 10 f tantalum capacitors from each supply to ground. signal routing should be short and direct to avoid parasitic effects. wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. when routing differential signals over a long distance, keep pcb traces close together, and twist any differential wiring to minimize loop area. doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 0.80 0.80 1.30 07752-056 figure 65. recommended pcb thermal attach pad dimensions (millimeters) 0.30 plated via hole 1.30 ground plane power plane bottom metal top metal 07752-057 figure 66. cross-section of 4-layer pcb showing thermal via co nnection to buried ground plane (dimensions in millimeters)
ada4932-1/ada4932-2 rev. a | page 25 of 28 high performance adc driving the ada4932-x is ideally suited for broadband dc-coupled applications. the circuit in figure 67 shows a front-end connection for an ada4932-1 driving an ad9245 , a 14-bit, 20 msps/40 msps/65 msps/80 msps adc, with dc coupling on the ada4932-1 input and output. (the ad9245 achieves its optimum performance when driven differentially.) the ada4932-1 eliminates the need for a transformer to drive the adc and performs a single-ended-to-differential conversion and buffering of the driving signal. the ada4932-1 is configured with a single 3.3 v supply and a gain of 1 for a single-ended input to differential output. the 53.6 termination resistor, in parallel with the single-ended input impedance of approximately 665 , provides a 50 termination for the source. the additional 25.5 (524.5 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. in this example, the signal generator has a 1 v p-p symmetric, ground-referenced bipolar output when terminated in 50 . the v ocm input is bypassed for noise reduction, and set externally with 1% resistors to maximize output dynamic range on the tight 3.3 v supply. because the inputs are dc-coupled, dc common-mode current flows in the feedback loops, and a nominal dc level of 0.84 v is present at the amplifier input terminals. a fraction of the output signal is also present at the input terminals as a common-mode signal; its level is equal to the ac output swing at the noninverting output, divided down by the feedback factor of the lower loop. in this example, this ripple is 0.5 v p-p [524.5/(524.5 + 511)] = 0.25 v p-p. this ac signal is riding on the 0.84 v dc level, produc- ing a voltage swing between 0.72 v and 0.97 v at the input terminals. this is well within the specified limits of 0.2 v to 1.5 v. with an output common-mode voltage of 1.65 v, each ada4932-1 output swings between 1.4 v and 1.9 v, opposite in phase, provid- ing a gain of 1 and a 1 v p-p differential signal to the adc input. the differential rc section between the ada4932-1 output and the adc provides single-pole low-pass filtering and extra buffering for the current spikes that are output from the adc input when its sha capacitors are discharged. the ad9245 is configured for a 1 v p-p full-scale input by connecting its sense pin to vref, as shown in figure 67. ada4932-1 3.3v 50? 499? 499 ? 25.5 ? 10k? 1% 511? 511? 33 ? 33 ? v ocm 2v p-p signal generator 1v p-p centered at ground 53.6 ? 0.1f 0.1f 10f + 0.1f 0.1f 10k? 1% 20pf vin? avdd vin+ vref sense agnd ad9245 v out, dm = 1v p-p v out, cm = 1.65v 07752-270 figure 67. ada4932-1 driving an ad9245 adc with dc-coupled input and output
ada4932-1/ada4932-2 rev. a | page 26 of 28 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 68. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vggd-2 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 69. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-1) dimensions shown in millimeters ordering guide model temperature range package description pa ckage option ordering quantity branding ada4932-1ycpz-r2 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 250 h1k ada4932-1ycpz-rl 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 5,000 h1k ada4932-1ycpz-r7 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 1,500 h1k ada4932-2ycpz-r2 1 ?40c to +105c 24-lead lfcsp_vq cp-24-1 250 ada4932-2ycpz-rl 1 ?40c to +105c 24-lead lfcsp_vq cp-24-1 5,000 ada4932-2ycpz-r7 1 ?40c to +105c 24-lead lfcsp_vq cp-24-1 1,500 1 z = rohs compliant part.
ada4932-1/ada4932-2 rev. a | page 27 of 28 notes
ada4932-1/ada4932-2 rev. a | page 28 of 28 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07752-0-8/09(a)

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